
Timothy Kelly Pmp
Seasoned SoC/ASIC functional director/manager and ASIC portfolio program manager (PMP Certified) with a demonstrated history of achieving results... | 8321 Nantahala Drive, Raleigh, United States
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Timothy Kelly Pmp’s Emails ti****@co****.com
Timothy Kelly Pmp’s Phone Numbers 1630568****
Social Media
Timothy Kelly Pmp’s Location 8321 Nantahala Drive, Raleigh, United States
Timothy Kelly Pmp’s Expertise Seasoned SoC/ASIC functional director/manager and ASIC portfolio program manager (PMP Certified) with a demonstrated history of achieving results in the Semiconductor and Telecommunications industries. Detail oriented with a proven track record of success building world class engineering teams and delivering ASIC/SoC/Systems with first pass silicon success. Skilled in Cryogenic hardware research and development, ASIC/SoC/FPGA development, OTN transport multi-service framers, People Management, Team Building, Project Management, Program Management, Digital Design and Verification, Lab Validation and Customer Relationships. Strong engineering leader with a reputation for integrity, perseverance and the ability to communicate effectively across all levels in the organization.
Timothy Kelly Pmp’s Current Industry Northrop Grumman
Timothy
Kelly Pmp’s Prior Industry
Intel
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Cortina Systems
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Inphi
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Rambus Labs Rambus
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Northrop Grumman
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Work Experience

Northrop Grumman
Program Manager, Advanced Electronics
Sun Mar 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Northrop Grumman
Project Manager
Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Mar 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Rambus Labs Rambus
SR Director of Engineering; Cryogenic Cold Memory Subsystems R&D
Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Sep 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Inphi
Senior Director of Engineering - Soc Design/Verification
Wed Oct 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Cortina Systems
Senior Director of Engineering Design/Verification SoC Development
Wed Oct 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Oct 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Cortina Systems
Senior Engineering Manager
Sun Oct 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jul 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Senior Design Engineering Manager
Thu Jan 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Technical Lead
Sat Jan 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)